Wafer bonding is the joining together of two or more semiconductor wafers upon which integrated circuitry has been formed to form a three-dimensional wafer stack. The wafer stack is subsequently diced into separate “stacked die,” each stacked die having multiple layers of integrated circuitry. Wafer stacking technology offers a number of potential benefits, including improved form factors, lower costs, enhanced performance, and greater integration through “system-on-chip” solutions. Potential applications for wafer stacking technology include, for example, high performance processing devices, video and graphics processors, as well as high density and high bandwidth memory chips.
Typically, to form a wafer stack, two wafers are oriented in face-to-face relationship, and conductors on one wafer are bonded to conductors on the other wafer. Each of the wafers—and, hence, the wafer stack—includes integrated circuitry for a number of integrated circuit die, or stacked die, which will ultimately be cut from the wafer stack. Electrical connections are formed through the backside of one of the wafers, and these backside connections will provide for the electrical connection of each stacked die with a next-level component, such as a package substrate, a circuit board, a motherboard, another integrated circuit device, a computer system, etc. The backside connections may comprise a number of conductive vias formed through one of the wafers, each via having one end extending to a conductor in the wafer (e.g., a conductor within an interconnect structure formed on that wafer) and having an opposing end coupled with a lead. For a flip-chip type package employing Controlled Collapse Chip Connection (“C4”) assembly techniques, these leads may comprise an array of solder bumps (or columns or other conductive elements).
The vias used to form the backside connections on a wafer stack, as described above, may be formed by a dry etch process (e.g., plasma etching). With these etching processes, however, it may be difficult to form vias having a high aspect ratio, which can limit the thickness of a wafer that can be etched through. Additional limitations on this technique of forming vias for backside connections include a lack of selectivity and the potential for overetching and/or an undesirable etch profile, as well as a sensitivity to variations in thickness of the wafer (which may be thinned at the backside).